The present invention relates to a technique for improving the reliability of a nonvolatile memory module and, particularly, to a technique that is effective for preventing data corruption due to disturb encountered in writing in small byte units.
In recent years, for semiconductor integrated circuit devices such as microcomputers incorporating a nonvolatile memory and microcomputers of a so-called flash memory built-in type, there is a need to mount a flash memory module that supports writing in small byte units.
FIG. 18 is an illustrative diagram showing a configuration example of a memory array 100 provided in a flash memory module examined by the present inventors.
In the memory array 100, as shown, SL driver circuits 101, MG drivers 102, and CG drivers 103 are provided. In order to decrease the areas of the drivers providing control signals, the memory array 100 is configured to have an array of memory cells MCs arranged in positions where signal lines (memory gate lines MGLs, control gate lines CGLs, source lines SLs) for selecting a memory cell MC intersect with signal lines (bit lines BLs) for transferring data that is input to or output from a memory cell MC.
In the above array configuration, a plurality of memory cells MCs coupled to one control gate line CGL share a memory gate line MGL and a source line SL. Therefore, for example, while the memory gate line MGL and the source line SL are selected, there are memory cells whose bit lines are deselected.
In this case, a hatched memory cell MC is selected, whereas memory cells MCs surrounded by bold lines are deselected. These deselected memory cells are placed in a write deselect state, but carry a weak write current, which may give rise to an unintended variation of a threshold voltage Vth (hereinafter referred to as disturb).
A technique as a countermeasure against such disturb is known, whereby a memory array is configured, for example, such that the number of memory cells MCs coupled to one memory gate line (MGL) is limited.